(1) Field of the Invention
The invention relates generally to data storage in semiconductor memory devices and more particularly, to memory devices equipped with sense amplifiers or additional read-out electronics such as Read Only Memory ROM, Flash memory, Random Access Memory (RAM), and also Magnetic RAM (MRAM) or even Ferroelectric RAM (FRAM). These memories are subsumed for brevity under the designation of Sense Electronics Endowed (SEE) memories. Even more particularly this invention is relating to SEE-memory devices with reduced power consumption by dynamical biasing of sense amplifiers during a low-power mode operation of such SEE-memory devices.
(2) Description of the Prior Art
Microprocessor systems can be found nowadays working in many devices, such as Personal Computers (PCs) especially modern portable notebook computers, in Personal Data Assistants (PDAs), mobile phones, navigation systems—mostly also used as portable devices, but also in many household appliances, in automobiles etc. and they all have Central Processing Units (CPUs) which need some sort of Random Access Memory (RAM) for their primary workspace (in RAM the code and data for the CPU are stored) usually implemented as semiconductor memory, wherein the contents of each byte can be directly and randomly accessed. Other types of memory chips, including ROMs and PROMs have this property as well, but only RAM chips are economically priced however they require power to maintain their content. The most common type of computer memory in current solid-state memory technology for main memory storage, which usually uses one transistor and a storage capacitor to represent a bit, is called Dynamic RAM (DRAM). Therein the capacitors must be energized hundreds of times per second in order to maintain the charges, representing the stored information as data. A data bus system is used for moving the information in and out of the RAM storage and an address bus addresses the storage location of the information data within the RAM. The RAM is usually organized in a grid or matrix configuration, where each bit is stored in its own data cell and each row and column has its own address. Another implementation called Static RAM (SRAM) is a type of RAM that holds data without need to refresh the stored content. An SRAM bit is made up of 4 to 8 transistors and is therefore very fast, with access times in the 10 to 30-nanosecond range but also power dissipating and expensive to produce. In comparison, DRAM only uses one transistor per memory cell and has access times, which are usually above 30 ns. SRAM does not require any refreshing operation and is easily handled, but is more expensive than DRAM and has a smaller capacity than DRAM comparing the same chip area. Because of these properties, SRAM is used to create a CPU's speed-sensitive cache, while DRAM is used for the larger system main storage RAM space. The memory internal operations during read, write, and refresh transactions are governed by a number of control signals allowing to strobe or clock addresses and data in and out, and to partially select, enable or inhibit these operations. All these operations are more or less power consuming, which leads especially with portable systems to reduced power-on times, as these systems are dependent from the energy capacity stored in their battery. These considerations hold especially for systems incorporating memory devices equipped with sense amplifiers or additional read-out electronics such as Read Only Memory ROM, Flash memory, Random Access Memory (RAM), and also Magnetic RAM (MRAM) or even Ferroelectric RAM (FRAM). These memories will in the following altogether be subsumed for brevity under the designation of Sense Electronics Endowed (SEE) memories. It is therefore important to reduce power consumption during operation of these systems, and especially the power consumption of the SEE-memory devices.
In the prior art, there are different technical approaches for achieving the goal of a reduction of power consumption. However these approaches use often solutions, which are somewhat technically complex and therefore also expensive in production. It would be advantageous to reduce the expenses in both areas. This is achieved by using a dynamical biasing of sense amplifiers during a low-power mode operation, when not in full service. Using the intrinsic advantages of that solution—as described later on in every detail—the circuit of the invention is realized with standard CMOS technology at low cost.
Preferred prior art realizations are implementing such related memory circuits in single chip or multiple chip solutions as integrated circuits. The permanent high power requirement and therefore high system costs are the main disadvantages of these prior art solutions. It is therefore a challenge for the designer of such devices and circuits to achieve a high-quality but also low-cost solution.
Several prior art inventions referring to such solutions describe related methods, devices and circuits, and there are also several such solutions available with various patents referring to comparable approaches, out of which some are listed in the following:
U.S. Pat. No. 6,118,439 (to Ho et al.) describes a low current voltage supply circuit for an LCD driver wherein a voltage supply circuit for an LCD driver employs two voltage dividers. A low current voltage divider includes resistive elements having a high resistance, thus providing a bias voltage with a low current. A high current voltage divider includes resistive elements having low resistances, thus providing a bias voltage with a high current. The high current voltage divider provides bias voltage levels with high current at the beginning of each time phase change. Thus, the liquid crystal display receives a high current when updating the bias voltage levels on the LCD, thereby producing a fast settling time. When the bias voltage levels are held constant, however, only the low current voltage divider provides the bias voltage levels to reduce power consumption. A halt mode prevents the liquid crystal display and driver from consuming any power by disconnecting both voltage dividers from the voltage source when in sleep mode. A voltage drop mode produces a reduction in the bias voltage levels by placing another voltage drop in series with the voltage dividers.
U.S. Pat. No. 6,624,669 (to Tsuchi) discloses a drive circuit and drive circuit system for capacitive load whereby said drive circuit includes a first field effect transistor having a source connected to an input terminal and a drain and a gate connected in common, a second field effect transistor having a drain to a first power supply terminal, a source connected to an output terminal and a gate connected to the gate of the first transistor, a first current control circuit connected between the first power supply terminal and the drain of the first transistor, a second current control circuit connected between the input terminal and a second power supply terminal, and a third current control circuit connected between the output terminal and the second power supply terminal. Accordingly, the gate of the second transistor is biased with a voltage that is deviated from an input voltage by a gate-source voltage of the first transistor, so that the second transistor operates in a source-follower fashion without oscillation. Thus, the drive circuit can be constructed without including a capacitor, and therefore, a required circuit area can be reduced.
U.S. Pat. No. 6,671,199 (to Maruyama) shows a data storage method for semiconductor integrated circuit, semiconductor integrated circuit, semiconductor device equipped with many of the semiconductor integrated circuits, and electronic apparatus using the semiconductor device whereby in said data storage method for memory cells that compose a semiconductor integrated circuit, a power supply potential VDD or a potential VL that is lowered from the power supply potential VDD by a threshold potential of Nch transistors is applied for each of the directions of the voltages that are applied to a ferroelectric capacitor in response to data to thereby perform writing. In the present invention, a semiconductor device equipped with a plurality of semiconductor integrated circuits described above is applied to FeRAMs or DRAMs, and the semiconductor device is used in a hand-carry type data terminal, a telephone and the like.
The basic RAM circuit is shown in FIG. 1 prior art in form of a modified circuit diagram (i.e. with graphical representation of the memory array as grid layout) with a storage (RAM) cell 10 as central component, wherein the information is stored as a single bit, in this case. Arranging these data storage cells 10 in form of a rectangular grid unfolds the core bit/word (X/Y) organized memory array element, with horizontal rows 12 and vertical columns 11 spanning a storage matrix 15 with Cartesian X and Y coordinates identifying the X/Y data cell location 10 and in such a way setting up the main storage area organized in bits (X) and words (Y). In technical terms the columns are designed as bit lines 11 and the rows as word lines 12, the storage (RAM) cells 10 can be implemented as single transistor-capacitor DRAM or multiple transistor SRAM cells, or even as formerly used magnetic cores or MRAM (Magnetic RAM) devices of late. This memory array is now addressed through the address bus system from the processor CPU with addresses made up of a Row Address 22 part and a Column Address 24 part, the Row Address 22 part being decoded in a Row Decoder 21 and the Column Address 24 part being decoded in the address part of a Column Decoder 25. The Row Decoder 21 is then activating the according word line 12, whereas the address part of the Column Decoder 25 activates the according bit line 11. Depending on the operation to be performed a Write, Read or Refresh cycle for the selected storage (RAM) cell 10 is then executed. Therefore Read/Write Circuits 40 are activated, performing the according bitwise data operations with the help of Sense Amplifiers 30 and acting on the particular storage (RAM) cells 10. The relevant data are delivered via said Column Decoder 25 too, having additionally a data part, connected to the Input/Output data bus system of the CPU. These data are therefore written into or read from the main memory array in parallel with the help of said Column Decoder 25 connected to said Read/Write Circuits 40 and these further connected on their part to said Sense Amplifiers 30 writing or reading the contents of the connected storage (RAM) cells 10. Refresh operations are essentially made up of a combination of Read/Write operations. The length of the address as shown in the figure is k bits and depends on the size of the addressable memory—defining also the bus width of the address bus, and the length of the data word as shown in the figure is M bits and depends on the CPU type—determining also the bus width of the data I/O bus.
Although these patents and papers describe circuits and/or methods close to the field of the invention they differ in essential features from the method, the system and especially the circuit introduced here.